📄 中文摘要
深度学习推理的硬件加速器中，数据流实现因其低延迟和高吞吐量能力而备受关注。在这些架构中，每个神经元被映射到专用的硬件单元，使其非常适合现场可编程门阵列（FPGA）的实现。以往的展开式实现主要集中在全连接网络，因为它们结构简单。然而，众所周知，卷积神经网络（CNNs）在图像处理、语音识别等领域表现出卓越的性能，其计算模式更复杂，包含卷积层、池化层等。针对CNNs，特别是在连续数据流场景下实现高效推理，需要专门的架构设计。传统的CNN加速器通常采用批处理模式，需要将输入数据缓存起来，引入额外的延迟。
📄 English Summary
Continuous-Flow Data-Rate-Aware CNN Inference on FPGA
Data flow implementations represent a key approach among hardware accelerators for deep learning inference, distinguished by their low latency and high throughput capabilities. Within these architectures, each neuron is meticulously mapped to a dedicated hardware unit, making them exceptionally well-suited for Field-Programmable Gate Array (FPGA) deployments. Prior unrolled implementations have predominantly focused on fully connected networks, primarily due to their inherent simplicity. However, it is widely recognized that Convolutional Neural Networks (CNNs) exhibit superior performance across diverse applications such as image processing and speech recognition, albeit with more complex computational patterns encompassing convolutional layers, pooling layers, and others. Achieving efficient inference for CNNs, particularly in continuous data flow scenarios, necessitates specialized architectural designs. Traditional CNN accelerators often operate in batch processing modes, requiring input data to be buffered, which inherently introduces additional latency. Conversely, continuous-flow processing demands that data can be input at a constant rate, with inference results continuously output, posing significant challenges for resource utilization and timing constraints. To realize data-rate-aware continuous-flow inference, designing highly efficient pipelined structures is crucial. These structures must ensure that each processing stage can operate at the input data rate, thereby preventing bottlenecks. This typically involves optimizing the storage and access patterns for convolutional kernels, feature maps, and weight data, leveraging the characteristics of FPGA on-chip memory resources such, as BRAM (Block RAM) and distributed RAM. Furthermore, data reuse mechanisms, such as sliding windows or line buffering techniques, are essential for reducing memory bandwidth requirements and enhancing computational efficiency.